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dc.contributor.authorLi, Sizhaozh_CN
dc.contributor.authorLin, Shanzh_CN
dc.contributor.authorChen, Demingzh_CN
dc.contributor.authorWong, W. Ericzh_CN
dc.contributor.authorGuo, Donghuzh_CN
dc.contributor.author郭东辉zh_CN
dc.date.accessioned2015-07-22T02:36:10Z
dc.date.available2015-07-22T02:36:10Z
dc.date.issued2014 September 17zh_CN
dc.identifier.citationProceedings - 8th International Conference on Software Security and Reliability - Companion, SERE-C 2014, 2014:247-251zh_CN
dc.identifier.other20144600189133zh_CN
dc.identifier.urihttps://dspace.xmu.edu.cn/handle/2288/86301
dc.descriptionConference Name:8th International Conference on Software Security and Reliability - Companion, SERE-C 2014. Conference Address: San Francisco, CA, United states. Time:June 30, 2014 - July 2, 2014.zh_CN
dc.description.abstractIn this paper, a cache coherence scheme in multi-processor is introduced. There is a specific model in each kind of software, cache coherence can be solved in AHB bus by these models. First, we use dynamic address mapping policy to realize data cache. Second, according to the randomness of application environment that set up shared cache adaptive configuration and management mechanism in the finite state machine timing sequence model of each kind of software, to ensure the system reliability. In order to support multi-tasking and multi-user operator system - Linux, the multi-processor must use shared memory technology, so this paper also introduced the memory management unit, and base on these, it focuses on how multi-processor and the AHB bus cooperate to ensure cache coherence of the whole system. We can use software execution model and hardware design to achieve instruction or data coherence between each cache and main memory. ? 2014 IEEE.zh_CN
dc.language.isoen_USzh_CN
dc.publisherInstitute of Electrical and Electronics Engineers Inc.zh_CN
dc.source.urihttp://dx.doi.org/10.1109/SERE-C.2014.47zh_CN
dc.subjectApplication programszh_CN
dc.subjectC (programming language)zh_CN
dc.subjectComputer operating systemszh_CN
dc.subjectLogic circuitszh_CN
dc.subjectMemory management unitszh_CN
dc.subjectMultiprocessing systemszh_CN
dc.subjectReliability analysiszh_CN
dc.subjectSoftware reliabilityzh_CN
dc.subjectSystems engineeringzh_CN
dc.titleAnalysis of system reliability for cache coherence scheme in multi-processorzh_CN
dc.typeConferencezh_CN


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