A high-speed high-resolution latch comparator for pipeline analog-to-digital converters

Abstract

A high-speed and high-resolution comparator intended to be implemented in a 12bit 100MHZ pipeline Analog-to-Digital Converter (ADC) for Frequency Wireless Local Area Network application is proposed. The designed comparator presents a rail-to-rail input range preamplifier without any capacitance required. This comparator with a novel architecture of output stage achieves very high speed at a low kickback noise. The simulation results using a 0.35 mu m TSMC CMOS process technology show that this comparator exhibits a propagation delay of 2.8ns and has a very high resolution for a rail-to-rail input signal range, while consumes only 1.0mW of power with 5.0V Voltage supply.