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A high-speed high-resolution latch comparator for pipeline analog-to-digital converters

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A high-speed high-resolution latch comparator for pipeline analog-to-digital converters.html (628bytes)
Date
2007
Author
Wang, Riyan
Li, Kaihang
李开航
Zhang, Jianqin
Nie, Bin
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  • 物理技术-已发表论文 [4196]
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Abstract
A high-speed and high-resolution comparator intended to be implemented in a 12bit 100MHZ pipeline Analog-to-Digital Converter (ADC) for Frequency Wireless Local Area Network application is proposed. The designed comparator presents a rail-to-rail input range preamplifier without any capacitance required. This comparator with a novel architecture of output stage achieves very high speed at a low kickback noise. The simulation results using a 0.35 mu m TSMC CMOS process technology show that this comparator exhibits a propagation delay of 2.8ns and has a very high resolution for a rail-to-rail input signal range, while consumes only 1.0mW of power with 5.0V Voltage supply.
Citation
2007 International Workshop on Anti-counterfeiting28-31
URI
https://dspace.xmu.edu.cn/handle/2288/69487

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