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dc.contributor.advisor王琳
dc.contributor.author林武
dc.date.accessioned2018-12-05T01:48:10Z
dc.date.available2018-12-05T01:48:10Z
dc.date.issued2017-12-28
dc.identifier.urihttps://dspace.xmu.edu.cn/handle/2288/170620
dc.description.abstract低密度奇偶校验码(LDPC)因其具有逼近香农限的纠错性能和相对较低的译码时延,因而被大多数通信系统采用为信道编码的实现方案。随着3GPP组织确定将LDPC码作为5G中移动宽带增强场景业务数据的长码块编码方案,对于LDPC译码器的应用研究进入了一个新的阶段。 而随着LDPC码的应用领域越来越广泛,单一码率的译码器已经不能满足常规通信系统的性能要求,为了适应信道的变化,达到最佳的传输效果,译码器往往需要支持多种码率的LDPC码。因此设计和实现高吞吐量和低硬件复杂度,而且支持多种码率的LDPC译码器是将LDPC码推向实用化的一个研究重点。 本文采用WiGig标准的四种码率的LDPC码型,码长为6...
dc.description.abstractThe low-density parity-check code (LDPC) is adopted by most communication systems as a channel coding implementation because of its error correction performance and relatively low decoding delay. As the 3GPP organization determines the LDPC code as long code block coding scheme for 5G mobile broadband enhanced scene service data, the research on application of LDPC decoder has entered a new stage....
dc.language.isozh_CN
dc.relation.urihttps://catalog.xmu.edu.cn/opac/openlink.php?strText=58616&doctype=ALL&strSearchType=callno
dc.source.urihttps://etd.xmu.edu.cn/detail.asp?serial=62263
dc.subject多码率
dc.subject低密度奇偶校验码
dc.subjectFPGA
dc.subjectmulti-rate
dc.subjectLDPC code
dc.subjectFPGA
dc.title多码率LDPC译码器的FPGA设计和实现
dc.title.alternativeDesign and Implementation of Multi-Rate LDPC Decoder Based on FPGA
dc.typethesis
dc.date.replied2017-05-19
dc.description.note学位:工程硕士
dc.description.note院系专业:信息科学与技术学院_工程硕士(电子与通信工程)
dc.description.note学号:23320141153253


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