一种低功耗的13位100MS/s采样保持电路
Low Power 13 b 100 MS/s Sample and Hold Circuit
Abstract
采用TSMC0.18μM1P6M CMOS工艺设计了一种高性能低功耗采样保持电路。该电路采用全差分折叠增益自举运算放大器和栅压自举开关实现。在3.3V电源电压下,该电路静态功耗仅为16.6MW。在100MHz采样频率时,输入信号在奈奎斯特频率下该电路能达到91db的Sfdr,其有效精度可以达到13位。 A high performance low power sample and hold circuit is designed based on TSMC0.18 μm 1P6M CMOS technology.In this circuit,a fully differential folded gain-boosted operational amplifier and bootstrapped switch is employed to meet the requirements.The circuit consumes only 16.6 mW static power with 3.3 V power supply,it can attain 91 dB SFDR when the input signal at Nyquist frequency with sampling rate of 100 MS/s,of which the effective number of bit(ENOB)can reach to 13 b.